But if the macro drives digital portion of the SoC, then its functionality is a must for FPGA prototyping. In this case also all the connections to the macro shall be brought out on ports at toplevel.

4. Experimental Results The example SoC design attributes are: 4M logic gates with 2M memory bits Targeted to run at 100MHz Maximum number of logic levels between Flop to Flop are 55 Number of clocks: ...