This article presents a 14-bit 200-Ms/s pipelined analog-to-digital converter (ADC) for wide input frequency range. The ADC adopts a sample-and-hold amplifier-less (SHA-less) 3.5-bit front-end stage.

A first stage of a SHA-less 12-bit 200 MSps pipeline analog-to-digital converter (ADC) is designed in this paper. A high speed and high precision comparator is designed in order to reduce the ...

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