Abstract: This paper describes the design of a 25 Gb/s energy-efficient CMOS optical receiver with high input sensitivity. By incorporating a current-boosting preamplifier with a dual-path ...

The prototype 6-bit 2.5-GS/s flash ADC was implemented in a 65-nm CMOS process and occupies a 0.12 mm 2 chip area, including offset calibration circuitry. The measured differential non-linearity (DNL) ...