The UEC 1.0 specification includes a modern RDMA approach, new transport protocols, and congestion control mechanisms designed for AI and HPC requirements.

"The Ultra Ethernet 1.0 Specification is the result of an outstanding collaboration of AI, HPC, and networking experts, system and silicon vendors, and network operators," added Hugh Holbrook ...

Posted: June 4, 2025 | Last updated: June 8, 2025 Bitfarms CEO Ben Gagnon explains the bitcoin miner's priority shift to HPC and AI from Bitcoin 2025.

READING, U.K. – June 2, 2025 – Aion Silicon (formerly Sondrel), a leading ASIC and SoC architecture partner, today announced it has secured a $12 million engagement to provide comprehensive design ...

SUNNYVALE, Calif., May 28, 2025--Advanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711), today announced Fan-Out Chip-on-Substrate ...

Wistron Corp (緯創), a contract manufacturer of servers and notebook computers, yesterday said that its new US plant would begin producing high-performance computing (HPC) devices for customers by the ...

High Performance Computing (HPC) High Performance Computing (HPC) provides multi-purpose, high performance computational resources that allow users to run many single or parallel jobs. HPC enables the ...

By Lakshmi Jain and Wei-Yu Ma The AI and HPC industries are rapidly shifting toward chiplet-based designs to achieve unprecedented levels of performance, as traditional monolithic system-on-chip (SoC) ...

But HPC, and the AI tools and data centers it powers, don’t run for free. Compute of the magnitude needed to run today’s AI tools (and scale them) demands lots of energy and physical space.

Galaxy and CoreWeave expanded their partnership, with CoreWeave committing to an additional 260 MW of critical IT load at Galaxy’s Helios data center, increasing total capacity to 393 MW for AI ...

JEDEC has announced the publication of its HBM4 standard: up to 8Gb/s across a 2048-bit memory interface, HBM4 offers up to 2TB/sec memory bandwidth.

AMD has just announced that its next-gen EPYC processor codenamed " Venice " is the first HPC product in the industry to be taped out and brought up on TSMC's advanced 2nm (N2) process technology.